The Blinking Computer: 2026 design

Draft of 13 Nov 2026. Markdown source for blinkingcomputer.org.

Summary

• 16-bit data and addresses, the ISA of emu/emu.c with all 16 opcode slots used: the two HCF slots become ROR and ASR.
• Registers P A B C in discrete transistors. Constants 0 1 2 3 by wiring. 64K words of memory in a Raspberry Pi Pico 2.
• The Pico also generates every timing edge. Nothing in the CPU makes its own edges, so the machine is correct at any speed from 0.01 Hz upwards.
• Everything stored is static: cross-coupled NPN pairs with the LED as the collector load. No DRAM, no capacitors in the signal path.
• One shared 16-bit bus between the register file, the ALU and the Pico.
• A 13-stage one-hot ring counter sequences one instruction. The Pico can step one phase, one instruction, or run continuously.
• About 800 transistors, of which about 760 carry an LED, on a one metre square panel.
• Programs in C, compiled to the existing Forth layer and assembler. Console on HDMI with a USB keyboard, or a laptop over USB.

Electrical rules

• Logic supply 5 V. The bus is pulled up to 3.3 V from the Pico's 3V3 pin, so the Pico never sees 5 V.
• Logic family is RTL with diode AND-OR inputs where fan-in needs it, never TTL: one transistor per gate.
• NPN throughout (2N3904 class for logic, BC337 or 2N2222 class for the line drivers that sink tens of mA). PNP is available if a block turns out cleaner with it, for example high-side line drivers.
• Every logic transistor has an LED in series with its collector resistor. The LED lights when the transistor conducts. Use red or classic yellow/green LEDs with Vf of 2.1 V or less; blue and white eat too much headroom.
• Collector load: LED plus 1k to 5 V, about 3 mA when on.
• Base resistor from an internal 5 V node: 10k. Base resistor from the 3.3 V bus: 47k, with at most 8 loads per bus line.
• Enables are done in the emitter. A transistor whose emitter sits on an "enable line" conducts only when that line is pulled to ground by its line driver. When the line floats up to 5 V the transistor is off whatever its base does.
• Wired-AND everywhere: a signal line is pulled up and any number of open-collector transistors may pull it low.

The bus

Sixteen lines BUS0..BUS15, active high, 1k pull-up to 3.3 V on each.

• CPU drivers are open collectors with their emitters on an enable line: register read transistors, ALU result drivers.
• Constant 0 1 2 3 are 16, 15, 15 and 14 diodes from the bus lines to a "constant select" line. When the line is pulled low the zero bits of the constant are pulled low.
• The Pico drives a 0 by setting the pin to output-low and a 1 by setting the pin to input. It never sources current.
• Loads on each bus line: the set transistors of P A B C IR IN0 IN1 and one indicator transistor, each through 47k. With 1k pull-ups the high level is about 2.9 V, above the Pico input threshold.
• Sixteen indicator transistors with LEDs show the bus.

Pico 2 pins

These are the CPU-facing pins. The I/O section explains why the final board is likely an RP2350B with more GPIO rather than a Pico 2.

Host communication is over USB serial, no pins.

Storage cells

Naming: a cell is transistors TA and TB, cross-coupled. Node NA is TA's collector, NB is TB's collector. Bit = 1 means TA on, NA low, NB high. The LED on TA's collector lights for 1, the LED on TB's collector lights for 0.

Register bit, 4 transistors

TSET can only write a 1. Clearing is done for the whole register by one transistor TLIFT in the return of the ER line: TLIFT is normally saturated (base via 1k to 5 V); pulling its base low floats the sixteen TA emitters and every bit falls to 0. A write is therefore: lift (all bits to 0), then set (the 1 bits from the bus).

TREAD conducts when the bit is 0 and RE is active, pulling the bus low. So the bus shows the register value.

Per register: 16 bits x 4 plus TLIFT, the WE driver and the RE driver = 67.

Latch bit, 3 transistors

IR, IN0 and IN1 are register bits without TREAD. Their outputs are taken straight from NA and NB, which gives both polarities free. Per latch: 16 x 3 plus lift and WE drivers = 50.

Flag and carry-in bits

eq0, lt0, carry and CIN are single latch bits (3 transistors each) with their own lift and set gating.

Line currents

• A WE line sinks up to 16 set transistors at about 3 mA, so 50 mA. An RE line sinks up to 16 bus pull-ups at 3.3 mA, so 53 mA. A lift transistor carries 16 cell currents, about 50 mA. Use BC337 or 2N2222 for these three per register and drive their bases with 2 to 4 mA.

Ring counter

Thirteen one-hot stages, each a master latch bit and a slave latch bit (3 transistors each).

• Masters: all lifted by CLR1, set by SET1 from the previous slave (set transistor base from NB of slave k-1, emitter on the SET1 line driver).
• Slaves: all lifted by CLR2, set by SET2 from their own master.
• Stage 0's master set input is slave 12. RESET lifts all slaves and masters then sets slave 0 through a set transistor with its base tied high and its emitter on RESET.
• The phase lines are the slave NB outputs, called F0..F12.

The master-slave arrangement means the SET1 strobe can be arbitrarily long without the token rippling through. 13 x 6 plus four line drivers plus reset = 84 transistors.

One instruction, phase by phase

The Pico performs one phase as: drive the bus if it is a data phase it owns; wait; sample the bus if it is an address or write-data phase; pulse CLR1 then SET1; release the bus; pulse CLR2 then SET2. The gap between phases is the speed control.

INC2 means: the instruction read through P and did not execute a direct write to P, exactly the emulator's rule.

Notes. - The carry flag is never read by the ALU directly. F8 copies the right carry-in into CIN, so updating the carry flag in F10 cannot disturb the result that is being written in the same strobe. - The increment phases force the ALU to ADD and force carry-in to 1 by wired-OR onto the control lines, and never touch the flags. - Non-executed instructions still walk every phase and still get INC2, as in the emulator.

ALU, per bit

Inputs a and not-a from IN0, b and not-b from IN1, cin from the bit below. Gates are RTL with diode AND-OR fan-in, one transistor each. Result drivers are open collectors onto the bus; a driver pulls its bus line low when the result bit is 0, so each driver's base wants the complement of the result, and in most cases that complement is already available.

• The three right shifts share the SHIFT drivers and differ only in what feeds bit 15: 0 for LSR, a15 for ASR, the carry for ROR. Three diodes and a couple of transistors.
• Every right shift writes bit 0 into the carry, so testing the low bit and multi-word shifts are free.
• eq0 is a 16-diode OR of the bus into one transistor, lt0 is BUS15, carry is cout of bit 15. The carry flag is written by ADC SBC and the shifts only. ADD and SUB leave it alone, as in the emulator.
• A resistor-threshold adder in the style of analogMajority.py would cut the adder to about 4 transistors per bit. Worth a 1-bit experiment but not the baseline, because it depends on LED forward voltages matching.

Decode and control

Decode uses both polarities of every IR bit, which the latch gives free. Diode AND of three IR bits plus one transistor makes one select line.

• src0: 8 select lines, src1: 8, dst: 4 for P A B C. 20 transistors.
• Each RE line is the OR of its terms gated by phase lines, for example RE_P = F0 or F2 or F11 or (F4 or F5 and not isrc0) and src0=P or ... . Diode networks plus the line driver.
• exec = cnd=always or (cnd=lt0 and lt0) or (cnd=eq0 and eq0) or (cnd=ne0 and not eq0). 4 transistors.
• MEMREQ = (F4 or F5) and isrc0, or (F6 or F7) and isrc1, or (F9 or F10) and idst and exec. 3 transistors.
• INC2 = reads through P and not (exec and direct write to P). 3 transistors.
• ALU op lines SUM AND SHIFT SUBSEL and the CIN select: 6 transistors.
• About 65 in total.

Instruction set

The rule is: as many instructions as the 16 opcode slots allow, provided each is cheap in transistors. Most instructions cost one open-collector driver per bit, about 17 transistors, and some cost almost nothing because they are wiring.

cc is 00 always, 01 lt0, 10 eq0, 11 ne0. The carry flag is a borrow flag after SBC: set when a is less than b, as the emulator has always done. Changes from emu/emu.c: ROR and ASR replace HCF0 and HCF1, and the right shifts now write the carry. HCF, exit and all I/O stay as writes to 0xFFFF, which the Pico services.

Things that are already free and need no opcode: move is ADD 0, compare is a write to a constant register, shift left is ADD with both sources the same, rotate left through carry is ADC with both sources the same, negate is 0 SUB x. Bitwise NOT is two instructions and would cost 17 transistors to add; it is the first candidate if a slot is ever freed.

• Regression gate: emu/utest.sh runs the 247 in/out tests embedded in sys.4th through forth2asm, asm, txt2bin and emu. It passes with no output on 13 Nov 2026 and must still do so after the emulator and assembler change.

Transistor budget

LEDs about 760. At 3 mA each the worst case is 2.2 A at 5 V, in practice about half light at once. A 5 V 3 A supply.

Pico firmware

C with the Pico SDK.

• Holds 64K x 16 bits of memory in SRAM, loaded over USB serial from the host using the existing asm.py and txt2bin flow.
• Tracks the phase number itself, resynchronising from PHASE0.
• Modes: run at a phase rate from 0.01 Hz to tens of kHz; step one phase; step one instruction; stop. Stepping can stop before or after the SET1 strobe so a class can see "value on the bus" and then "value latched".
• Implements the OS calls (exit, getc, putc, and so on) exactly as emu.c does, over USB serial.

The Pico as logic analyser

The build will have mistakes in it, and schools building it will have more. So the Pico checks the hardware against the reference emulator at every phase, not just when it services memory, and stops on the first disagreement.

The Pico runs a copy of emu.c in lock step with the ring counter. It samples the bus in every phase, whether or not it is a memory phase, because the bus carries something checkable in almost all of them:

It also checks MEMREQ in every phase against what the instruction says it should be, which tests the decode of isrc0, isrc1, idst and exec, and it checks that PHASE0 comes back exactly every 13 phases, which tests the ring.

The latches themselves are checked indirectly: a bad IN0 shows up at F10, a bad IR shows up as wrong operands, wrong MEMREQ or a wrong result, and a bad register shows up the next time it is read. Between them these checks cover every transistor in the machine within one or two instructions of it going wrong.

On a mismatch the Pico holds the clock, so the LEDs freeze at the failing phase for probing, and reports over USB serial: the instruction address and its disassembly in the asm.py notation, the phase name, the expected and seen bus values in binary with the differing bits marked, and the suspect block from the table above. Commands then let you continue ignoring the error, single step onwards, or reset. The same machinery gives self-tests that need no program: walk a 1 across the bus, write and read back each register with random words, and run the ring on its own.

Software stack

Three layers, each visible to a student and each runnable on the emulator and on the hardware.

C is the right top layer: it is standard, it is the original portable assembler, it has no large runtime of its own, and it is what schools and the museum will recognise.

How the C compiler works

Decision, 13 Nov 2026: port chibicc rather than write a compiler from scratch or retarget TinyCC. chibicc is about nine thousand lines of C under the MIT licence, supports most of C11, and was written as a teaching compiler with one feature per commit, which suits the project. The port lives in chibicc/ with the changes listed in chibicc/BLINKING.md; the front end is untouched apart from type sizes, and codegen.c is new.

Each C function becomes one colon definition. Expressions are evaluated on the data stack, so a + b is literally the Forth +. A function's arguments and locals are a frame on the data stack addressed through a frame pointer cell, with the words enter, leave, fload, fstore and faddr in emu/clib.4th doing the work. Names defined in C get a c_ prefix so they cannot collide with runtime words; a C declaration with no definition names a runtime word directly, which is how putc and putd are called. printf with a literal format is expanded at compile time into the runtime's output words, so no formatting code runs on the machine.

Type sizes follow the machine, which is word addressed with no bytes:

Not yet supported: floating point, variadic functions other than printf, structs passed or returned by value, bitfields, alloca and variable length arrays.

Testing: emu/ctest.sh compiles and runs every program in emu/ctest/ and compares the output with the // out line in the source; emu/clibtest.sh runs the tests embedded in clib.4th; emu/utest.sh is unchanged and still passes. The emulator's SBC sets the carry on a borrow, which the runtime words and the ISA table above now both state.

System calls

A write to 0xFFFF is a system call serviced by the Pico, with arguments in the low words of memory as emu.c does now. The C library is therefore mostly on the Pico: putchar, getchar, puts, printf's formatting, string functions, and anything else that would cost more machine code than it teaches. A student can still write their own printf in C if the lesson is about printf.

Input and output

The Pico 2 has 26 GPIO and the CPU interface uses 23. The RP2350's video output, HSTX, needs eight of them, GPIO 12 to 19, so a single Pico 2 cannot do both. Two ways forward:

• One RP2350B board instead of the Pico 2. The RP2350B is the same silicon in a larger package with 48 GPIO, and the same SDK. The Waveshare RP2350-PiZero (about ten dollars) has a mini HDMI socket driven by HSTX, a 40-pin header exposing 28 GPIO, a second USB port that can be a host for a keyboard, a microSD slot and a USB-C port for the laptop link. That is a complete console in one board. The WeAct RP2350B core board exposes all 48 GPIO with HSTX and takes a DVI adapter.
• Two Pico 2s. One is the memory and clock, the other drives a display and keyboard, linked by a UART on two pins. Cheaper to understand, slightly more to build.

Decision, 13 Nov 2026: one RP2350B board with HDMI, so the machine stands alone with its own screen and keyboard, which is the demonstration that matters. It costs about £15 in the UK, 15 percent of the budget, and buys both the video output and the spare pins. A laptop over USB serial remains the fallback and the debug channel.

The display

The screen is a character map, as on the BBC Micro, and it lives in the machine's own memory so a program can draw by writing to it.

• The RP2350B board drives the monitor with its HSTX peripheral: DMA feeds a stream from the Pico's SRAM to HSTX, which does the TMDS encoding in hardware, and the board routes the eight HSTX pins through series resistors to the mini HDMI socket. It is a DVI signal, which every HDMI monitor accepts; there is no audio. The SDK's dvi_out_hstx_encoder example streams a 640 by 480 frame buffer this way.
• There is no frame buffer here. Core 1 of the Pico builds each scan line just in time from the character map and the glyph table, 80 characters of 8 by 8 pixels per line, 480 lines, while core 0 is the CPU's memory, clock and analyser. That is a few hundred table lookups per line at 150 MHz, well within budget.
• The character map is 80 by 30 words of the CPU's 64K address space, 2400 words at 0xF000. Because the Pico is the memory, a write to that range simply lands on the screen on the next frame. Each word is a glyph number in the low 8 bits, so 7-bit ASCII draws text with the BBC Micro font and the upper 128 glyphs are free for a program to define. The high bits are attributes: bit 15 inverse video, bits 8 to 10 a foreground colour from eight.
• The glyph table is also memory, 256 glyphs of 8 words each, one pixel row per word in the low byte, 2048 words at 0xE800. Writing eight words redefines a character, which is how a program draws shapes, sprites and bar charts.
• The system calls putc and putstr still exist and keep a cursor, so a plain C program prints as it would anywhere; scrolling moves the character map.
• The font is the 8 by 8 Acorn MOS font, 96 printable characters of 8 bytes each from the OS 1.20 ROM at &C000. It is reproduced in several open source projects, for example the bbcelite disassembly, but its copyright belongs to Acorn's successors and no licence for it has been found, so the shipped default should be a redrawn 8 by 8 font in the same spirit with the BBC glyphs as an option the builder loads.

A class that cannot read the LEDs from the back of the room can also have the registers and phase drawn on the screen beside the program's output.

Physical form

• A flat panel one metre by one metre, hung on a wall at home or in a museum, transportable to schools for demonstrations. Built as two hinged halves, each one metre by half a metre, it folds for the car and still shows everything when open.
• The layout follows the architecture so a viewer can read it: the ring counter as a row of thirteen lights across the top, the bus as a row of sixteen below it, the four registers as four rows of sixteen, then IR, IN0 and IN1, then the ALU, with the flags and decode in a column at one side and the Pico at an edge.
• Sixteen identical bit-slice boards, one per bit, each carrying that bit of every register and latch, the ALU slice and the bus indicator. About fifty transistors per slice in a column roughly 60 mm wide, so one slice is one board and a panel is a row of sixteen plus a control board. Identical boards keep the cost down and let a school build one slice at a time.
• About 800 transistors and 760 LEDs at 3 mA need a 5 V 3 A supply. The Pico and its video run from the same 5 V.
• One unit is intended for the Centre for Computing History in Cambridge, which means replaceable boards, a bill of materials and build notes good enough for someone else to repair it.

Budget

The target is £100 for everything, so a school can build one. Rough UK prices in November 2026, quantities as needed for one machine with a small surplus:

The boards are the item that decides it. Sixteen identical slices keep the per-board price down, and a school that already has a laminator can build the earlier plan's laminated-sheet version of a slice for almost nothing, at the cost of more wiring.

Build order

1. One register bit on a breadboard with the Pico driving CLR and SET. Confirm the 47k base from a 3.3 V bus sets the bit, that lift clears it, and that it holds for a day.
2. One full register of 16 bits with its three line drivers. Pico writes random words and reads them back.
3. One ring stage pair, then the whole ring, stepped by the Pico.
4. One ALU bit slice, then 16, fed from IN0 and IN1.
5. Decode, then run the Forth system with the compare mode on.

Open questions

• Whether blue LEDs from the existing stock can be used anywhere. They drop 2.8 to 3.0 V and leave only about 2 V at a collector node.
• Whether to add OUT and FREQ style control writes next to the 0xFFFF OS call. Cheap in firmware, nothing in hardware.
• The physical form: laminated A4 sheets, one per block, were the earlier plan.
• Supply voltage above 5 V. 12 V is possible and would suit a diode-only fast adder, but costs power in 740 LED loads and needs level shifting at the bus. Decide after the 1-bit ALU experiment.